The present invention relates to a method of manufacturing high-density integrated circuit semiconductor devices exhibit reliable, adherent, low resistance, accurately-aligned contacts to source, drain, and gate electrode region of active devices, such as MOS transistors formed in or on a semiconductor substrate, by utilizing self-aligned, refractory metal silicide (xe2x80x9csalicidexe2x80x9d) processing methodology. The present invention has particular utility in manufacturing high-density integration semiconductor devices, including multi-level devices, with design rules of 0.18 xcexcm and below, e.g., 0.15 xcexcm and below.
The escalating requirements for high density and performance associated with ultra-large scale integration (ULSI) devices necessitate design rules of 0.18 xcexcm and below, such as 0.15 xcexcm and below, with increased transistor and circuit speeds, high reliability, and increased manufacturing throughput. The reduction of design features, e.g., of source and drain regions, and gate electrodes of transistors formed in or on a common semiconductor substrate, challenges, the limitations of conventional contact and interconnection technology, including conventional photolithographic, etching, and deposition techniques.
Self-aligned techniques are conventionally employed for forming large-scale and ultra-small dimensioned integrated semiconductor devices. As device dimensions decrease into the deep sub-micron range, both vertically and laterally, many problems arise, especially those caused by an increase in sheet resistance of the contact areas to the source and drain regions and junction leakage as junction layer thickness decreases. To overcome this problem, the use of self-aligned, highly electrically conductive refractory metal silicides, i.e., salicides, has become commonplace in the manufacture of integrated circuit semiconductor devices comprising, e.g., MOS type transistors. Another technique employed in conjunction with refractory metal silicide technology is the use of lightly-doped source and drain extensions formed just at the edge of the gate region, while more heavily-doped source and drain regions, to which ohmic contact is to be provided, are laterally displaced away from the gate by provision of sidewall spacers on opposing sides of the gate electrode.
Salicide processing involves deposition of a metal that forms a compound with silicon, but does not react with silicon oxides, nitrides, or oxynitrides under normal processing conditions. Refractory metals commonly employed in salicide processing include platinum (Pt), titanium (Ti), nickel (Ni), and cobalt (Co), each of which forms very low resistivity phases with silicon (Si), e.g., PtSi2, TiSi2, NiSi and CoSi2. In practice, the refractory metal is deposited in uniform thickness over all exposed upper surface features of a Si wafer, preferably by means of physical vapor deposition (PVD) from an ultra-pure sputtering target and an ultra-high vacuum, multi-chamber DC magnetron sputtering system. In MOS transistor formation, deposition is generally performed both after gate etch and after source/drain junction formation. In a less common variant, source/drain junction formation is effected subsequent to refractory metal layer deposition via dopant diffusion through the refractory metal layer into the underlying semiconductor. In either case, after deposition, the refractory metal layer blankets the top surface of the gate electrode, typically formed of heavily-doped polysilicon, the silicon oxide, nitride, or oxynitride sidewall spacers on the opposing side surfaces of the gate electrode, the silicon oxide isolation regions formed in the silicon substrate between adjacent active device regions, and the exposed surfaces of the substrate where the source and drain regions are formed or will be subsequently formed. As a result of thermal processing, e.g., a rapid thermal annealing process (RTA) performed in an inert atmosphere, the refractory metal reacts with underlying Si to form electrically conductive silicide layer portions on the top surface of the polysilicon gate electrode and on the exposed surfaces of the substrate where source and drain regions are or will be formed. Unreacted portions of the refractory metal layer, e.g., on the silicon oxide, nitride, or oxynitride sidewall spacers and the silicon oxide isolation regions, are then removed, as by a wet etching process selective to the metal silicide portions. In some instances, e.g., with Co, a first RTA step may be performed at a relatively lower temperature in order to form first-phase CoSi which is then subjected to a second RTA step performed at a relatively high temperature to convert the first-phase CoSi to second-phase, lower resistivity CoSi2.
Illustrated in FIGS. 1(A)-1(E) are steps in a typical salicide process, illustratively CoSi2, for manufacturing MOS transistors and CMOS devices according to the conventional art. The term xe2x80x9csemiconductor substratexe2x80x9d as employed throughout the present disclosure and claims, denotes a Si-containing wafer, e.g., a monocrystalline Si wafer, or an epitaxial Si-containing layer formed on a semiconductor substrate comprising at least one region 1 of a first conductivity type. It will be appreciated that for P-MOS transistors, region 1 is n-type and for N-MOS transistors, region 1 is p-type. It is further understood that the substrate may comprise pluralities of n- and p-type regions arrayed in a desired pattern, as for example, in CMOS devices.
Referring more particularly to FIG. 1(A), reference numeral 1 indicates a region or portion of a Si-containing semiconductor substrate of a first conductivity type (p or n), fabricated as a MOS transistor precursor 2 for use in a salicide process scheme. Precursor 2 is processed, as by conventional techniques not described here in detail, in order to not unnecessarily obscure the primary significance of the following description. Precursor 2 comprises a plurality of, illustratively two, isolation regions 3 and 3xe2x80x2 of a silicon oxide, e.g., shallow trench isolation (STI) regions, extending from the substrate surface 4 to a prescribed depth below the surface. A gate insulator layer 5, typically comprising a silicon oxide layer about 25-50 xc3x85 thick, is formed on substrate surface 4. Gate electrode 6, typically of heavily-doped polysilicon, is formed over a portion of silicon oxide gate insulator layer 5, and comprises opposing side surfaces 6xe2x80x2, 6xe2x80x2, and top surface 6xe2x80x3. Blanket layer 7 of an insulative material, typically an oxide, nitride, or oxynitride of silicon, is then formed to cover all exposed portions of substrate surface 4 and the exposed surfaces of the various features formed thereon or therein, inter alia, the opposing side surfaces 6xe2x80x2, 6xe2x80x2 and top surface 6xe2x80x3 of gate electrode 6 and the upper surface of STI regions 3, 3xe2x80x2. The thickness of blanket insulative layer 7 is selected so as to provide sidewall spacers, 7xe2x80x2, 7xe2x80x2 of desired width (see below) on each of the opposing side surfaces 6xe2x80x2, 6xe2x80x2 of the gate electrode 6.
Referring now to FIG. 1(B), MOS precursor structure 2 is then subjected to an anisotropic etching process, as by reactive plasma etching utilizing a fluorocarbon- or fluorohydrocarbon-based plasma comprising argon (Ar) and at least one reactive gaseous species selected from CF4 and CHF3, for selectively removing the laterally extending portions of insulative layer 7 and underlying portions of the gate oxide layer 5, whereby sidewall spacers 7xe2x80x2, 7xe2x80x2 of desired width profile are formed along the opposing side surfaces 6xe2x80x2, 6xe2x80x2 of gate electrode 6. According to conventional processing methodology, the entire thickness of the selected portions of insulative layer 7 and any underlying portions of gate oxide layer 5 are removed during the plasma etching process. Endpoint monitoring of the plasma etching process is typically achieved spectroscopically, as by loss of characteristic oxygen peak of the plasma atmosphere upon complete consumption of the blanket insulative layer 7 and/or the gate oxide layer 5.
Adverting to FIG. 1(C), moderately- to heavily-doped source and drain junction regions 8 and 9 of conductivity type opposite that of the substrate (or epitaxial layer on a suitable substrate) are then formed in substrate region 1, as by conventional ion implantation (the details of which are omitted for brevity), with sidewall spacers 7xe2x80x2, 7xe2x80x2 acting as implantation masks and setting the lateral displacement length of moderately- to heavily-doped regions 8 and 9 from the respective proximal edges 6xe2x80x2, 6xe2x80x2 of gate electrode 6.
With reference to FIG. 1(D), in a following step, the thus-formed structure with implanted moderately- to heavily-doped source/drain regions 8, 9 is subjected to a conventional high temperature treatment, typically rapid thermal annealing (RTA), for effecting activation and diffusion of the implanted dopant species, thereby also forming lightly-doped, shallower depth source/drain extension regions, 8xe2x80x2, 9xe2x80x2 laterally extending from the respective proximal edges of the moderately- to heavily-doped source/drain regions 8, 9 to just beneath the neighboring edge 6xe2x80x2 of gate electrode 6. It should be recognized, however, that the above-described method for forming source/drain regions including lightly-doped extensions is merely illustrative. Equivalently performing source/drain structures may be formed by alternative process schemes, e.g., by first lightly implanting substrate 1 with dopant impurities of second conductivity type prior to sidewall spacer formation, with the implanted regions extending to just beneath the respective edges of the gate electrode, followed by selective heavy implantation of the lightly-doped implant (e.g., after sidewall spacer formation) to form heavily-doped source/drain regions appropriately spaced from the gate electrode by the light-doped (extension) implants.
With continued reference to FIG. 1(D), a layer 10 of a refractory metal metal, typically Pt, Co, Ni, or Ti, is formed, as by DC sputtering, to cover the exposed upper surfaces of precursor structure 2. Following refractory metal layer 10 deposition, a thermal treatment, typically rapid thermal annealing (RTA), is performed at a temperature and for a time sufficient to convert metal layer 10 to the corresponding electrically conductive metal silicide, e.g., PtSi2, CoSi2, NiSi, or TiSi2. Since the refractory metal silicide forms only where metal layer 10 is in contact with the underlying silicon, the unreacted portions of metal layer 10 formed over the silicon oxide isolation regions 3 and 3xe2x80x2 and silicon nitride sidewall spacers 7xe2x80x2, 7xe2x80x2 are selectively removed, as by a wet etch process.
Referring now to FIG. 1(E), the resulting structure after reaction and removal of unreacted metal comprises metal silicide layer portions 11 and 12, 12xe2x80x2 respectively formed over gate electrode 6 and heavily-doped source and drain regions 8 and 9. Further processing may include, inter alia, formation of metal contact and dieletric insulator layers. However, as is evident from FIG. 1(E), the lower surfaces of the metal silicide layer 12, 12xe2x80x2 portions formed by the above-described methodology are rough at the silicide-silicon interfaces, disadvantageously resulting in penetration of the underlying silicon substrate 1 by the silicide. Such penetration or xe2x80x9cspikingxe2x80x9d of the silicon in the region below the source and drain junction regions 8 and 9, illustratively shown at 13 and 13xe2x80x2, can cause local shorting of the junctions, thereby resulting in junction leakage. The effect of junction penetration or spiking is greatest with metals such as Co, which have relatively high silicon consumption ratios. Junction penetration or spiking can be moderated or at least minimized and improved junction integrity provided by increasing the junction depth of source and drain regions 8 and 9 or by providing a thinner refractory metal layer, thereby reducing silicon consumption during silicidation. However, neither of these alternatives is satisfactory: the former approach runs counter to the trend toward smaller device dimensions, both vertically and laterally, in order to increase transistor switching speeds, and the latter approach results in an increase in metal silicide sheet resistance attendant its decrease in thickness.
Another drawback associated with the conventional processing methodology is poor quality metal silicide formation arising from the anisotropic plasma etching of the blanket insulative layer 7 utilized for forming the sidwall spacers 7xe2x80x2, 7xe2x80x2. As indicated supra, according to conventional processing methodology, the plasma etching process is terminated only when the selected portions of the blanket insulative layer 7 and/or any underlying gate insulator (i.e., oxide) layer 5 are completely removed, i.e., the oxide spacer etch stops at the substrate surface, typically of silicon. However, the conventionally utilized anisotropic plasma etch processing employing fluorocarbon and/or fluorohydrocarbon gas(es) disadvantageously results in formation of a carbonaceous polymeric residue on the silicon substrate surface and/or structural damage thereto, either of which results in poor quality metal silicide formation during subsequent processing.
A number of techniques for reducing leakage in ultra-shallow junctions employed in MOSFET type semiconductor devices have been proposed, such as are disclosed in U.S. Pat. Nos. 4,835,112; 5,208,472; 5,536,684; and 5,691,212. Such techniques, however, materially add to process complexity and include such steps as germanium implantation to retard dopant diffusion, provision of multiple dielectrics at the edges of the gate electrode, formation of a CoSi2xe2x80x94TiNx bi-layer followed by removal of the TiNx layer and ion implantation of the remaining CoSi2 layer, and formation of an amorphous silicon layer on a silicon MOS precursor and subsequent implantation, oxidation, annealing, etc., steps.
Thus, there exists a need for a simplified methodology for forming self-aligned silicide (i.e., salicide) contacts to ultra-thin transistor source and drain regions which provide low contact sheet resistance, absence of spiking, no or at least minimal junction leakage, and easy compatability with conventional process flow for the manufacture of MOS-based semiconductor devices, e.g., CMOS devices. Moreover, there exists a need for an improved process for fabricating high quality, low junction leakage MOS transistor-based devices which provides increased manufacturing throughput and product yield.
An advantage of the present invention is a method of manufacturing a high density, sub-micron dimensioned integrated semiconductor device with an improved self-aligned contact structure.
Another advantage of the present invention is a method of forming MOS-based semiconductor devices and transistors with metal silicide-contacted shallow source and drain regions exhibiting very low junction leakage.
Still another advantage of the present invention is an improved method for forming refractory metal silicide electrical contacts to silicon semiconductor surfaces.
Yet another advantage of the present invention is a MOS transistor having very low sheet resistance self-aligned metal silicide contacts an ultra-shallow source and drain junction regions with very low junction leakage.
Additional advantages and other features of the present invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the present invention. The advantages of the present invention may be realized and obtained as particularly pointed out in the appended claims.
According to an aspect of the present invention, the foregoing and other advantages are achieved in part by a method of manufacturing a semiconductor device, which method comprises the sequential steps of:
(a) providing a semiconductor substrate of a first conductivity type and having a surface;
(b) forming a thin gate insulator layer in contact with the substrate surface;
(c) forming a gate electrode on a portion of the gate insulator layer, the gate electrode comprising first and second opposing side surfaces and a top surface;
(d) forming a blanket layer of an insulative material on exposed portions of the thin gate insulator layer on the substrate surface and on the first and second opposing side surfaces and the top surface of the gate electrode;
(e) selectively removing, by anisotropically etching for a preselected interval, a major amount of the thickness of the blanket layer of insulative material from the substrate surface portions and from the top surface of the gate electrode, thereby (1) forming a tapered width insulative sidewall spacer on each of the first and second opposing side surfaces of the gate electrode and (2) leaving a residual thickness of the layer of insulative material on portions of the substrate surface adjacent to sidewall spacers and on the top surface of the gate electrode;
(f) introducing dopant impurities of a second, opposite conductivity type into the residual thickness portions of a layer of insulative material on the portions of the substrate surface adjacent the sidewall spacers to thereby form a pair of spaced-apart, shallow depth, source/drain regions in the substrate, each of the pair of source and drain regions extending to just beneath a respective proximal edge of the gate electrode; and
(g) removing the residual thickness portions of the layer of insulative material to expose substantially undamaged portions of the substrate surface adjacent the sidewall spacers and to expose the top surface of the gate electrode.
In embodiments according to the present invention, step (a) comprises providing a silicon substrate; step (b) comprises forming a silicon oxide gate insulating layer about 25-50 xc3x85 thick; step (c) comprises forming the gate electrode from an electrically conductive material comprising heavily-doped polysilicon; step (d) comprises forming a blanket layer of an insulative material comprising an oxide, nitride, or oxynitride of silicon of a preselected thickness for forming the sidewall spacers with a preselected width; step (e) comprises anisotropically etching the blanket layer of insulating material for a preselected interval in a reactive plasma comprising a fluorocarbon or fluorohydrocarbon compound selected from CF4 and CHF3; and step (f) comprises selectively implanting the first conductivity type substrate with dopant impurity-containing ions of second type.
According to embodiments of the present invention, step (d) comprises forming a blanket, i.e., conformal, layer of insulative material comprising a layer of silicon oxide; step (e) comprises leaving a residual thickness of the silicon oxide layer on the substrate surface portions adjacent the sidewall spacers and on the top surface of the gate electrode; step (f) comprises selectively implanting an n-type silicon substrate with boron-containing p-type dopant impurities or selectively implanting a p-type silicon substrate with phosphorus- or arsenic-containing n-type dopant impurities: and step (g) comprises removing the residual silicon oxide layer portions by etching treatment with dilute aqueous HF.
According to a further embodiment of the present invention, the method further comprises the steps of:
(h) forming a blanket layer of a metal in contact with the exposed portions of the substrate surface adjacent the sidewall spacers, the top surface of the gate electrode, and the sidewall spacers;
(i) reacting the blanket metal layer to selectively form an electrically conductive silicide of the metal in contact with the portions of the silicon substrate surface adjacent the sidewall spacers and the top surface of the polysilicon gate electrode; and
(i) selectively removing unreacted portions of the blanket metal layer, including portions in contact with the sidewall spacers.
According to embodiments of the present invention, step (h) comprises forming the blanket metal layer from a refractory metal selected from the group consisting of platinum, titanium, cobalt, and nickel; and step (i) comprises thermally reacting the refractory metal layer with underlying silicon of the substrate.
According to another aspect of the present invention, a method of manufacturing an MOS semiconductor device comprises the sequential steps of:
(a) providing a silicon semiconductor substrate of first conductivity type and having a surface;
(b) forming a thin silicon oxide gate insulator layer in contact with the substrate surface;
(c) forming a gate electrode comprising heavily-doped polysilicon on a portion of the gate insulator layer, the gate electrode comprising first and second opposing side surfaces and a top surface;
(d) forming a blanket layer of an insulative material comprising an oxide, nitride, or oxynitride of silicon on exposed portions of the thin gate insulator layer on the substrate and on the first and second opposing side surfaces and the top surface of the gate electrode;
(e) selectively removing, by anisotropically etching for a preselected interval, a major amount of the thickness of the blanket layer of insulative material from the substrate surface portions and from the top surface of the gate electrode, thereby (1) forming a tapered width insulative sidewall spacer on each of the first and second opposing side surfaces of the gate electrode and (2) leaving a residual thickness of the layer of insulative material on portions of the substrate surface adjacent the sidewall spacers and on the top surface of the gate electrode;
(f) introducing dopant impurities of a second, opposite conductivity type into the residual thickness portions of the layer of insulative material on the portions of the substrate adjacent the sidewall spacers to thereby form a pair of spaced-apart, shallow depth, source/drain regions in the substrate, each of the pair of source/drain regions extending to just beneath a respective proximal edge of the gate electrode;
(g) removing the residual thickness portions of the layer of insulative material to expose substantially undamaged portions of the substrate surface adjacent the sidewall spacers and to expose the top surface of the gate electrode;
(h) forming a blanket layer of a metal in contact with the exposed portions of the substrate surface adjacent the sidewall spacers, the top surface of the gate electrode, and the sidewall spacers;
(i) reacting the blanket metal layer to selectively form an electrically conductive silicide of the metal at portions thereof in contact with the exposed portions of the silicon substrate surface adjacent the sidewall spacers and the top surface of the polysilicon gate electrode; and
(j) selectively removing unreacted portions of the blanket metal layer, including portions in contact with the sidewall spacers.
In embodiments according to the present invention, step (e) comprises anisotropically etching the blanket layer of insulative material for a preselected interval in a reactive plasma comprising a fluorocarbon or a fluorohydrocarbon compound selected from CF4 and CHF3; step (f) comprises selectively implanting the first conductivity silicon substrate with dopant impurity-containing ions of second conductivity type; step (h) comprises forming the blanket metal layer from a refractory metal selected from platinum, titanium, cobalt, and nickel; and step (i) comprises thermally reacting the blanket metal layer with underlying silicon and/or polysilicon.
According to further embodiments of the present invention, step (d) comprises forming a blanket layer of an insulative material comprising a layer of silicon oxide; step (e) comprises leaving a residual thickness of the silicon oxide layer on the portions of the substrate surface adjacent the sidewall spacers and on the top surface of the gate electrode: and step (g) comprises removing the residual silicon oxide layer portions by etching treatment with dilute aqueous HF.
According to yet another aspect of the present invention, silicon-based MOS-type transistor devices formed by the method of the above-enumerated steps (a)-(i) are provided.
Additional advantages and aspects of the present invention will become readily apparent to those skilled in the art from the following detailed description, wherein only the preferred embodiment of the present invention is shown and described, simply by way of illustration of the best mode contemplated for carrying out the method of the present invention. As will be described, the present invention is capable of other and different embodiments, and its several details are susceptible of modification in various obvious respects, all without departing from the spirit of the present invention. Accordingly, the drawing and description are to be regarded as illustrative in nature, and not as limitative.